Surefire Report

Summary

[Summary] [Package List] [Test Cases]


Tests Errors Failures Skipped Success Rate Time
546 0 2 3 99.1% 8312 s

Note: failures are anticipated and checked for with assertions while errors are unanticipated.


Package List

[Summary] [Package List] [Test Cases]


Package Tests Errors Failures Skipped Success Rate Time
cpu.Frodo4 4 0 0 0 100% 60.37 s
cpu.Testsuite 6 0 2 3 16.7% 855.2 s
vic 18 0 0 0 100% 226.3 s
libsidplay.components.mos6526 8 0 0 0 100% 0.002 s
libsidplay.components.keyboard 32 0 0 0 100% 0.054 s
cpu 232 0 0 0 100% 4303 s
cia 230 0 0 0 100% 2673 s
sid 16 0 0 0 100% 193.0 s

Note: package statistics are not computed recursively, they only sum up all of its testsuites numbers.

cpu.Frodo4

- Class Tests Errors Failures Skipped Success Rate Time
FrodoTest(C64C) 2 0 0 0 100% 30.19 s
FrodoTest(C64) 2 0 0 0 100% 30.18 s

cpu.Testsuite

- Class Tests Errors Failures Skipped Success Rate Time
WolfgangLorentzTest(C64C) 3 0 0 3 0% 1.003 s
WolfgangLorentzTest(C64) 3 0 2 0 33.3% 854.2 s

vic

- Class Tests Errors Failures Skipped Success Rate Time
ViceVICTest(C64) 9 0 0 0 100% 113.2 s
ViceVICTest(C64C) 9 0 0 0 100% 113.1 s

libsidplay.components.mos6526

- Class Tests Errors Failures Skipped Success Rate Time
MOS6526TodDividerTest(C64C) 4 0 0 0 100% 0.001 s
MOS6526TodDividerTest(C64) 4 0 0 0 100% 0.001 s

libsidplay.components.keyboard

- Class Tests Errors Failures Skipped Success Rate Time
KeyboardGhostingTest(C64C) 16 0 0 0 100% 0.039 s
KeyboardGhostingTest(C64) 16 0 0 0 100% 0.015 s

cpu

- Class Tests Errors Failures Skipped Success Rate Time
ViceCpuTest(C64C) 67 0 0 0 100% 949.7 s
ViceInterruptOracleTest(C64) 6 0 0 0 100% 0.009 s
ViceInterruptTest(C64) 37 0 0 0 100% 1235 s
ViceCpuTest(C64) 67 0 0 0 100% 965.9 s
ViceInterruptOracleTest(C64C) 6 0 0 0 100% 0.009 s
ViceInterruptTest(C64C) 37 0 0 0 100% 1153 s
ViceCpuExitContractTest(C64C) 6 0 0 0 100% 0.003 s
ViceCpuExitContractTest(C64) 6 0 0 0 100% 0 s

cia

- Class Tests Errors Failures Skipped Success Rate Time
CIATest(C64) 2 0 0 0 100% 31.60 s
ViceCIATest(C64C) 81 0 0 0 100% 1163 s
ViceCIAAdditionalContractTest(C64C) 22 0 0 0 100% 0.084 s
CIATest(C64C) 2 0 0 0 100% 31.52 s
ViceCIATest(C64) 81 0 0 0 100% 1178 s
ViceCIAPortsTest(C64C) 10 0 0 0 100% 134.7 s
ViceCIAAdditionalContractTest(C64) 22 0 0 0 100% 0.067 s
ViceCIAPortsTest(C64) 10 0 0 0 100% 133.8 s

sid

- Class Tests Errors Failures Skipped Success Rate Time
SidTuneTest(C64C) 8 0 0 0 100% 96.55 s
SidTuneTest(C64) 8 0 0 0 100% 96.47 s

Test Cases

[Summary] [Package List] [Test Cases]

FrodoTest(C64C)

testDADB 14.12 s
testDE00all 15.08 s

CIATest(C64)

detectCIA6526 10.78 s
timerBCountsA 19.82 s

FrodoTest(C64)

testDADB 14.12 s
testDE00all 15.07 s

WolfgangLorentzTest(C64C)

testDisk1
+ [ Detail ]
 0 s
- WolfgangLorentz requires C64Model.C64 -
testDisk2
+ [ Detail ]
 0 s
- WolfgangLorentz requires C64Model.C64 -
testDisk3
+ [ Detail ]
 0 s
- WolfgangLorentz requires C64Model.C64 -

ViceCpuTest(C64C)

runViceProgramToVerifiedTerminal[0: CPU/64doc/dadc.prg] 15.77 s
runViceProgramToVerifiedTerminal[1: CPU/64doc/dincsbc-deccmp.prg] 14.87 s
runViceProgramToVerifiedTerminal[2: CPU/64doc/dincsbc.prg] 14.53 s
runViceProgramToVerifiedTerminal[3: CPU/64doc/droradc.prg] 15.16 s
runViceProgramToVerifiedTerminal[4: CPU/64doc/dsbc-cmp-flags.prg] 14.24 s
runViceProgramToVerifiedTerminal[5: CPU/64doc/dsbc.prg] 14.01 s
runViceProgramToVerifiedTerminal[6: CPU/Acid800/cpu_bugs.prg] 12.24 s
runViceProgramToVerifiedTerminal[7: CPU/Acid800/cpu_clisei.prg] 12.32 s
runViceProgramToVerifiedTerminal[8: CPU/Acid800/cpu_decimal.prg] 12.56 s
runViceProgramToVerifiedTerminal[9: CPU/Acid800/cpu_flags.prg] 12.23 s
runViceProgramToVerifiedTerminal[10: CPU/Acid800/cpu_illegal.prg] 12.57 s
runViceProgramToVerifiedTerminal[11: CPU/Acid800/cpu_insn.prg] 12.15 s
runViceProgramToVerifiedTerminal[12: CPU/Acid800/cpu_timing.prg] 12.50 s
runViceProgramToVerifiedTerminal[13: CPU/Acid800/cpu_timing_ntsc.prg] 13.02 s
runViceProgramToVerifiedTerminal[14: CPU/asap/cpu_ane.prg] 13.14 s
runViceProgramToVerifiedTerminal[15: CPU/asap/cpu_anx.prg] 13.15 s
runViceProgramToVerifiedTerminal[16: CPU/asap/cpu_decimal.prg] 28.67 s
runViceProgramToVerifiedTerminal[17: CPU/asap/cpu_las.prg] 12.13 s
runViceProgramToVerifiedTerminal[18: CPU/asap/cpu_shx.prg] 12.26 s
runViceProgramToVerifiedTerminal[19: CPU/bclark/decimalmode.prg] 20.07 s
runViceProgramToVerifiedTerminal[20: CPU/cpuport/test1.prg] 11.81 s
runViceProgramToVerifiedTerminal[21: CPU/decimalmode/adc00.prg] 11.81 s
runViceProgramToVerifiedTerminal[22: CPU/decimalmode/adc01.prg] 11.82 s
runViceProgramToVerifiedTerminal[23: CPU/decimalmode/adc02.prg] 11.83 s
runViceProgramToVerifiedTerminal[24: CPU/decimalmode/adc10.prg] 11.83 s
runViceProgramToVerifiedTerminal[25: CPU/decimalmode/adc11.prg] 11.85 s
runViceProgramToVerifiedTerminal[26: CPU/decimalmode/adc12.prg] 11.86 s
runViceProgramToVerifiedTerminal[27: CPU/decimalmode/arr00.prg] 11.81 s
runViceProgramToVerifiedTerminal[28: CPU/decimalmode/arr01.prg] 11.82 s
runViceProgramToVerifiedTerminal[29: CPU/decimalmode/arr02.prg] 11.82 s
runViceProgramToVerifiedTerminal[30: CPU/decimalmode/arr10.prg] 11.81 s
runViceProgramToVerifiedTerminal[31: CPU/decimalmode/arr11.prg] 11.81 s
runViceProgramToVerifiedTerminal[32: CPU/decimalmode/arr12.prg] 11.82 s
runViceProgramToVerifiedTerminal[33: CPU/decimalmode/sbc00.prg] 11.83 s
runViceProgramToVerifiedTerminal[34: CPU/decimalmode/sbc01.prg] 11.82 s
runViceProgramToVerifiedTerminal[35: CPU/decimalmode/sbc02.prg] 11.81 s
runViceProgramToVerifiedTerminal[36: CPU/decimalmode/sbc10.prg] 11.84 s
runViceProgramToVerifiedTerminal[37: CPU/decimalmode/sbc11.prg] 11.82 s
runViceProgramToVerifiedTerminal[38: CPU/decimalmode/sbc12.prg] 11.80 s
runViceProgramToVerifiedTerminal[39: CPU/decimalmode/sbcEB00.prg] 12.31 s
runViceProgramToVerifiedTerminal[40: CPU/decimalmode/sbcEB01.prg] 12.22 s
runViceProgramToVerifiedTerminal[41: CPU/decimalmode/sbcEB02.prg] 12.39 s
runViceProgramToVerifiedTerminal[42: CPU/decimalmode/sbcEB10.prg] 12.23 s
runViceProgramToVerifiedTerminal[43: CPU/decimalmode/sbcEB11.prg] 12.20 s
runViceProgramToVerifiedTerminal[44: CPU/decimalmode/sbcEB12.prg] 12.25 s
runViceProgramToVerifiedTerminal[45: CPU/decimalmode/isc00.prg] 11.90 s
runViceProgramToVerifiedTerminal[46: CPU/decimalmode/isc01.prg] 11.83 s
runViceProgramToVerifiedTerminal[47: CPU/decimalmode/isc02.prg] 11.85 s
runViceProgramToVerifiedTerminal[48: CPU/decimalmode/isc03.prg] 11.89 s
runViceProgramToVerifiedTerminal[49: CPU/decimalmode/isc10.prg] 11.83 s
runViceProgramToVerifiedTerminal[50: CPU/decimalmode/isc11.prg] 11.83 s
runViceProgramToVerifiedTerminal[51: CPU/decimalmode/isc12.prg] 11.83 s
runViceProgramToVerifiedTerminal[52: CPU/decimalmode/isc13.prg] 11.83 s
runViceProgramToVerifiedTerminal[53: CPU/decimalmode/rra00.prg] 11.81 s
runViceProgramToVerifiedTerminal[54: CPU/decimalmode/rra01.prg] 11.84 s
runViceProgramToVerifiedTerminal[55: CPU/decimalmode/rra02.prg] 11.82 s
runViceProgramToVerifiedTerminal[56: CPU/decimalmode/rra03.prg] 11.92 s
runViceProgramToVerifiedTerminal[57: CPU/decimalmode/rra10.prg] 11.96 s
runViceProgramToVerifiedTerminal[58: CPU/decimalmode/rra11.prg] 11.84 s
runViceProgramToVerifiedTerminal[59: CPU/decimalmode/rra12.prg] 11.83 s
runViceProgramToVerifiedTerminal[60: CPU/decimalmode/rra13.prg] 11.93 s
runViceProgramToVerifiedTerminal[61: CPU/decimalmode/scanner.prg] 112.3 s
runViceProgramToVerifiedTerminal[62: CPU/hmc6502/AllSuiteA.prg] 12.51 s
runViceProgramToVerifiedTerminal[63: CPU/jsrselfmod/jsr.prg] 11.82 s
runViceProgramToVerifiedTerminal[64: CPU/sha/shaabsy1.prg] 12.15 s
runViceProgramToVerifiedTerminal[65: CPU/sha/shazpy1.prg] 12.16 s
runViceProgramToVerifiedTerminal[66: CPU/shs/shsabsy1.prg] 12.21 s

ViceCIATest(C64C)

ciaVarious14MatchesReference 12.71 s
timeOfDayHammerfistZeroWrites 12.21 s
cascadedTimerBMatchesReferencePAL 16.45 s
timeOfDayAlternateAlarmAfterResetMatchesReference 12.97 s
timeOfDayInvalidTenthsMatchReference 14.77 s
ciaVarious11MatchesReference 11.55 s
ciaVarious8MatchesReference 11.82 s
cia1SdrIcrBaud4Through127 28.31 s
ciaVarious5MatchesReference 11.56 s
timeOfDayInvalidHoursMatchReference 17.42 s
cia1InterruptControlReadsMatchReference 11.87 s
shiftRegisterInterruptControlOneShotMatchesReference 12.95 s
ciaVarious2MatchesReference 11.44 s
timeOfDayAlarmSetsInterruptFlag 12.91 s
timeOfDayInvalidSecondsMatchReference 17.76 s
timeOfDayStabilityPAL 14.89 s
timeOfDayFroggerClockContinues 12.30 s
timerReadsAndInterruptTimingMatchReference 12.55 s
timeOfDayHammerfistRegisterSequence 11.91 s
cia2SdrIcrBaud0Through127 28.83 s
zeroLatchReloadControlCombinationsMatchReference 11.90 s
ciaTimerInterruptWindowsMatchReferenceNTSC 13.01 s
cia1SdrIcrBaud0 12.25 s
cia1SdrIcrBaud3 12.26 s
ciaVarious15MatchesReference 21.65 s
timeOfDayHoursMatchBasicReference 13.57 s
cia1SdrIcrBaud1Through127 28.73 s
cia2SdrIcrBaud0 12.27 s
cia2SdrIcrBaud3 12.26 s
pendingInterruptFlagsSurviveMaskingContinuous 12.64 s
shiftRegisterSerialPortOneShotMatchesReference 12.94 s
timeOfDayAlarmAfterEveryResetMatchesReference 12.88 s
ciaVarious12MatchesReference 11.42 s
cia2Dd0dNmiAcknowledgementTimingMatchesReference 12.56 s
ciaVarious9MatchesReference 11.49 s
cascadedTimerBMatchesReferenceNTSC 18.53 s
shiftRegisterSerialPortContinuousMatchesReference 13.03 s
ciaVarious6MatchesReference 11.56 s
timeOfDayPowerUpStateMatchesReference 12.48 s
timeOfDayAlarmConditionWhenSettingAlarm 12.43 s
timeOfDaySlurpyAlarmHourOnly 12.91 s
timerOutputControlsPortBPins 11.54 s
ciaVarious3MatchesReference 11.80 s
ciaTimerInterruptWindowsMatchReferencePAL 12.84 s
timeOfDayRepeatedCia2AlarmMatchesReference 12.98 s
timeOfDayReadLatchMatchesReference 13.18 s
cia2SdrIcrBaud4Through127 28.27 s
serialRegisterBackToBackWritesMatchReference 12.20 s
cia1TimerCounterReadsMatchReference 11.87 s
zeroLatchReloadValueSweepMatchesReference 11.89 s
ciaVarious3AMatchesReference 11.89 s
cia2SdrIcrBaud19 12.57 s
cia2SdrIcrBaud39 12.34 s
ciaVarious13MatchesReference 11.43 s
timeOfDayAlarmConditionWhenSettingTime 12.18 s
timeOfDayWriteStopAndRestartMatchReference 12.64 s
cia1SdrIcrBaud19 12.22 s
cia1SdrIcrBaud39 12.55 s
shiftRegisterInterruptControlContinuousMatchesReference 13.38 s
timeOfDayInvalidMinutesMatchReference 17.35 s
ciaVarious10MatchesReference 11.54 s
ciaVarious7MatchesReference 11.45 s
cia1SdrIcrBaud0Through127 28.83 s
timeOfDayStabilityNTSC 15.62 s
serialRegisterInitialTransferMatchesReference 12.22 s
ciaVarious4MatchesReference 11.50 s
ciaVarious1MatchesReference 11.37 s
cia2SdrIcrBaud1Through127 28.60 s
serialRegisterCompletionDelayMatchesReference 12.27 s
ciaRegistersMirrorEvery16Bytes 11.93 s
timeOfDayAmPmWritesMatchBasicReference 11.88 s
timeOfDayInputDividerHzsync0 17.31 s
timeOfDayInputDividerHzsync1 14.85 s
timeOfDayInputDividerHzsync2 17.39 s
timeOfDayInputDividerHzsync3 14.85 s
timeOfDayInputDividerHzsync4 16.21 s
timeOfDayInputDividerHzsync5 17.67 s
pendingInterruptFlagsSurviveMaskingOneShot 13.01 s
timeOfDaySlurpyAlarmAllRegisters 12.85 s
timeOfDayRepeatedCia1AlarmMatchesReference 13.80 s
indexedStoreAcknowledgesInterruptFlags 11.83 s

ViceInterruptOracleTest(C64)

repeatingProgramRequiresTwoProgressChanges 0 s
terminalGreenRequiresCorrectPcAndHold 0 s
transientGreenNeverPasses 0 s
referenceMismatchNeverPassesAndResetsHold 0 s
exitRecognizerRequiresPublishedIoExitAndSelfJump 0.009 s
schedulerResetIsNeverSilentlyAccepted 0 s

ViceCIAAdditionalContractTest(C64C)

sdrNeedsBothCompleteSamplePointers 0.002 s
sdrRejectsSpaceAbortedOrIncompleteBaudSweep 0 s
invalidSnapshotsAreRejected 0 s
badOrUnreviewedResourcesFailClosed 0.001 s
greenBeforeCascadeCompletionIsNotSuccess 0 s
cascadeFailureCannotBeHiddenByCyclingGreenBorder 0.044 s
observedLoopBytesMustStillMatch 0 s
timerComparesFirstAndLastOf960Bytes 0.001 s
sdrChecksBothThousandByteResults 0.003 s
ramUnderD7ffNeverActsAsAnExitLatch 0 s
parsedReferenceIsIndependentOfCallerPrgArray 0 s
ambiguousCompletionAndTruncatedReferencesAreRejected 0.001 s
allFourteenNormalSdrVariantsHaveContracts 0.023 s
unusedJmpSelfIsNotTimerCompletion 0.001 s
sdrPreservesEarlierSweepFailures 0.002 s
cascadeNeedsTerminalSuccessAndFullReference 0.001 s
sdrPrematureGreenAndDataAreNotCompletion 0 s
missingFileIsNotSkipped 0.001 s
changedIdentityIsRejectedEvenAtCompletion 0 s
resultOwnsNoLiveMemoryAndReportsMismatchAddress 0 s
timerRequiresAllEightConfigurations 0.002 s
timerSourceFailureCannotBecomePass 0.001 s

MOS6526TodDividerTest(C64C)

fiftyHzModeAdvancesAfterFiveInputPulses 0 s
switchingAfterFifthPulseSkipsTheImminentIncrement 0 s
switchingAfterFourthPulseAllowsTheNextIncrement 0 s
sixtyHzModeAdvancesAfterSixInputPulses 0 s

CIATest(C64C)

detectCIA6526 10.79 s
timerBCountsA 19.74 s

ViceInterruptTest(C64)

verifyInterruptProgram[0: IRQ dummy instruction fetch] 15.08 s
verifyInterruptProgram[1: simultaneous CIA IRQ/NMI] 18.54 s
verifyInterruptProgram[2: branch IRQ recognition] 12.91 s
verifyInterruptProgram[3: branch NMI recognition] 13.20 s
verifyInterruptProgram[4: CIA interrupt acknowledgement IRQ] 12.96 s
verifyInterruptProgram[5: CIA interrupt acknowledgement NMI] 12.90 s
verifyInterruptProgram[6: CIA1 near-IRQ acknowledgement] 12.49 s
verifyInterruptProgram[7: CIA2 near-NMI acknowledgement] 12.13 s
verifyInterruptProgram[8: VIC IRQ acknowledgement via RMW] 15.80 s
verifyInterruptProgram[9: pending unacknowledged VIC IRQ after RTI] 12.48 s
verifyInterruptProgram[10: pending VIC IRQ after PLP] 15.46 s
verifyInterruptProgram[11: pending VIC IRQ after CLI/SEI] 12.44 s
verifyInterruptProgram[12: IRQ during DMA, pattern 1] 58.40 s
verifyInterruptProgram[13: IRQ during DMA, sprite pattern 1b] 58.47 s
verifyInterruptProgram[14: IRQ during DMA, pattern 2] 58.27 s
verifyInterruptProgram[15: IRQ during DMA, sprite pattern 2b] 58.33 s
verifyInterruptProgram[16: IRQ during DMA, pattern 3] 58.34 s
verifyInterruptProgram[17: IRQ during DMA, sprite pattern 3b] 58.30 s
verifyInterruptProgram[18: IRQ during DMA, pattern 4] 58.85 s
verifyInterruptProgram[19: IRQ during DMA, sprite pattern 4b] 58.21 s
verifyInterruptProgram[20: IRQ during DMA, pattern 5] 58.76 s
verifyInterruptProgram[21: IRQ during DMA, sprite pattern 5b] 58.55 s
verifyInterruptProgram[22: IRQ during DMA, pattern 6] 58.38 s
verifyInterruptProgram[23: IRQ during DMA, sprite pattern 6b] 58.22 s
verifyInterruptProgram[24: IRQ during DMA, pattern 7] 58.31 s
verifyInterruptProgram[25: IRQ during DMA, sprite pattern 7b] 58.36 s
verifyInterruptProgram[26: NMI during DMA, pattern 6] 58.70 s
verifyInterruptProgram[27: NMI during DMA, sprite pattern 6b] 58.60 s
verifyInterruptProgram[28: CIA IRQ/NMI delay sweep] 15.53 s
verifyInterruptProgram[29: CIA1 timing, small reload] 13.99 s
verifyInterruptProgram[30: CIA1 timing, one-shot small reload] 14.72 s
verifyInterruptProgram[31: CIA1 timer IRQ 255] 13.57 s
verifyInterruptProgram[32: CIA1 one-shot timer IRQ 255] 14.03 s
verifyInterruptProgram[33: CIA2 timer NMI 255] 13.58 s
verifyInterruptProgram[34: CIA2 one-shot timer NMI 255] 14.03 s
verifyInterruptProgram[35: CIA2 small-latch NMI arrives] 13.60 s
verifyInterruptProgram[36: CIA2 small-latch one-shot NMI arrives] 14.36 s

KeyboardGhostingTest(C64C)

noKeyReadbacksCoverAllSignedBytePinPatterns 0 s
longChainsReachAFixedPoint 0 s
originalCiaPortsReferenceTablesStillMatch 0.001 s
disconnectedComponentsDoNotMerge 0 s
joystickInputsRemainLowAndPropagateThroughContacts 0 s
reverseScanDistinguishesInputsFromDrivenHighOutputs 0 s
shiftLockStillWinsWhereOrdinaryLeftShiftDoesNot 0 s
singleContactsRetainTheirDirectReadbacks 0.032 s
readsNeverAddPhantomKeysToThePhysicalSet 0 s
restoreIsNeverTreatedAsAMatrixContact 0 s
releasingAnySdfContactRemovesThePhantom 0 s
sdfGeneratesGhostInBothForwardScanModes 0.001 s
everyThreeCornerRectangleCompletesThroughTheMatrix 0.004 s
legacyReadOverloadsRemainUsable 0 s
samePortReadsFollowKeyboardConnections 0 s
contentionRequiresTwoDistinctActivelyLowOutputs 0 s

SidTuneTest(C64C)

loadPSidTest 12.24 s
detectSidModelTest 16.89 s
loadPrgTest 12.33 s
loadMusStereoTest 10.81 s
loadMusTest 10.38 s
loadPSid3SidTest 11.63 s
loadPSidStereoTest 10.90 s
loadP00Test 10.36 s

ViceCIATest(C64)

ciaVarious14MatchesReference 12.63 s
timeOfDayHammerfistZeroWrites 12.01 s
cascadedTimerBMatchesReferencePAL 22.38 s
timeOfDayAlternateAlarmAfterResetMatchesReference 13.19 s
timeOfDayInvalidTenthsMatchReference 14.90 s
ciaVarious11MatchesReference 11.58 s
ciaVarious8MatchesReference 11.59 s
cia1SdrIcrBaud4Through127 29.63 s
ciaVarious5MatchesReference 11.56 s
timeOfDayInvalidHoursMatchReference 17.95 s
cia1InterruptControlReadsMatchReference 11.99 s
shiftRegisterInterruptControlOneShotMatchesReference 13.05 s
ciaVarious2MatchesReference 11.55 s
timeOfDayAlarmSetsInterruptFlag 12.55 s
timeOfDayInvalidSecondsMatchReference 17.40 s
timeOfDayStabilityPAL 15.21 s
timeOfDayFroggerClockContinues 12.22 s
timerReadsAndInterruptTimingMatchReference 12.65 s
timeOfDayHammerfistRegisterSequence 11.94 s
cia2SdrIcrBaud0Through127 30.14 s
zeroLatchReloadControlCombinationsMatchReference 11.85 s
ciaTimerInterruptWindowsMatchReferenceNTSC 12.70 s
cia1SdrIcrBaud0 12.26 s
cia1SdrIcrBaud3 12.28 s
ciaVarious15MatchesReference 22.95 s
timeOfDayHoursMatchBasicReference 13.76 s
cia1SdrIcrBaud1Through127 30.27 s
cia2SdrIcrBaud0 12.27 s
cia2SdrIcrBaud3 12.27 s
pendingInterruptFlagsSurviveMaskingContinuous 13.18 s
shiftRegisterSerialPortOneShotMatchesReference 13.06 s
timeOfDayAlarmAfterEveryResetMatchesReference 13.20 s
ciaVarious12MatchesReference 11.47 s
cia2Dd0dNmiAcknowledgementTimingMatchesReference 12.78 s
ciaVarious9MatchesReference 11.57 s
cascadedTimerBMatchesReferenceNTSC 13.86 s
shiftRegisterSerialPortContinuousMatchesReference 13.22 s
ciaVarious6MatchesReference 11.49 s
timeOfDayPowerUpStateMatchesReference 12.00 s
timeOfDayAlarmConditionWhenSettingAlarm 12.11 s
timeOfDaySlurpyAlarmHourOnly 13.15 s
timerOutputControlsPortBPins 11.54 s
ciaVarious3MatchesReference 11.81 s
ciaTimerInterruptWindowsMatchReferencePAL 12.69 s
timeOfDayRepeatedCia2AlarmMatchesReference 13.22 s
timeOfDayReadLatchMatchesReference 13.00 s
cia2SdrIcrBaud4Through127 29.85 s
serialRegisterBackToBackWritesMatchReference 12.23 s
cia1TimerCounterReadsMatchReference 11.87 s
zeroLatchReloadValueSweepMatchesReference 11.86 s
ciaVarious3AMatchesReference 11.89 s
cia2SdrIcrBaud19 12.36 s
cia2SdrIcrBaud39 12.31 s
ciaVarious13MatchesReference 11.46 s
timeOfDayAlarmConditionWhenSettingTime 11.55 s
timeOfDayWriteStopAndRestartMatchReference 12.73 s
cia1SdrIcrBaud19 12.33 s
cia1SdrIcrBaud39 12.25 s
shiftRegisterInterruptControlContinuousMatchesReference 13.08 s
timeOfDayInvalidMinutesMatchReference 17.73 s
ciaVarious10MatchesReference 11.55 s
ciaVarious7MatchesReference 11.59 s
cia1SdrIcrBaud0Through127 30.42 s
timeOfDayStabilityNTSC 15.72 s
serialRegisterInitialTransferMatchesReference 12.17 s
ciaVarious4MatchesReference 11.20 s
ciaVarious1MatchesReference 11.47 s
cia2SdrIcrBaud1Through127 30.33 s
serialRegisterCompletionDelayMatchesReference 12.28 s
ciaRegistersMirrorEvery16Bytes 11.94 s
timeOfDayAmPmWritesMatchBasicReference 11.89 s
timeOfDayInputDividerHzsync0 18.12 s
timeOfDayInputDividerHzsync1 15.30 s
timeOfDayInputDividerHzsync2 17.70 s
timeOfDayInputDividerHzsync3 15.31 s
timeOfDayInputDividerHzsync4 16.52 s
timeOfDayInputDividerHzsync5 18.63 s
pendingInterruptFlagsSurviveMaskingOneShot 12.81 s
timeOfDaySlurpyAlarmAllRegisters 13.14 s
timeOfDayRepeatedCia1AlarmMatchesReference 14.10 s
indexedStoreAcknowledgesInterruptFlags 11.61 s

ViceCpuTest(C64)

runViceProgramToVerifiedTerminal[0: CPU/64doc/dadc.prg] 15.74 s
runViceProgramToVerifiedTerminal[1: CPU/64doc/dincsbc-deccmp.prg] 14.60 s
runViceProgramToVerifiedTerminal[2: CPU/64doc/dincsbc.prg] 14.57 s
runViceProgramToVerifiedTerminal[3: CPU/64doc/droradc.prg] 15.15 s
runViceProgramToVerifiedTerminal[4: CPU/64doc/dsbc-cmp-flags.prg] 14.43 s
runViceProgramToVerifiedTerminal[5: CPU/64doc/dsbc.prg] 13.81 s
runViceProgramToVerifiedTerminal[6: CPU/Acid800/cpu_bugs.prg] 12.33 s
runViceProgramToVerifiedTerminal[7: CPU/Acid800/cpu_clisei.prg] 12.30 s
runViceProgramToVerifiedTerminal[8: CPU/Acid800/cpu_decimal.prg] 12.67 s
runViceProgramToVerifiedTerminal[9: CPU/Acid800/cpu_flags.prg] 12.31 s
runViceProgramToVerifiedTerminal[10: CPU/Acid800/cpu_illegal.prg] 12.70 s
runViceProgramToVerifiedTerminal[11: CPU/Acid800/cpu_insn.prg] 12.34 s
runViceProgramToVerifiedTerminal[12: CPU/Acid800/cpu_timing.prg] 12.33 s
runViceProgramToVerifiedTerminal[13: CPU/Acid800/cpu_timing_ntsc.prg] 13.08 s
runViceProgramToVerifiedTerminal[14: CPU/asap/cpu_ane.prg] 12.85 s
runViceProgramToVerifiedTerminal[15: CPU/asap/cpu_anx.prg] 12.83 s
runViceProgramToVerifiedTerminal[16: CPU/asap/cpu_decimal.prg] 29.98 s
runViceProgramToVerifiedTerminal[17: CPU/asap/cpu_las.prg] 12.35 s
runViceProgramToVerifiedTerminal[18: CPU/asap/cpu_shx.prg] 12.24 s
runViceProgramToVerifiedTerminal[19: CPU/bclark/decimalmode.prg] 20.28 s
runViceProgramToVerifiedTerminal[20: CPU/cpuport/test1.prg] 11.98 s
runViceProgramToVerifiedTerminal[21: CPU/decimalmode/adc00.prg] 12.02 s
runViceProgramToVerifiedTerminal[22: CPU/decimalmode/adc01.prg] 11.93 s
runViceProgramToVerifiedTerminal[23: CPU/decimalmode/adc02.prg] 11.93 s
runViceProgramToVerifiedTerminal[24: CPU/decimalmode/adc10.prg] 11.91 s
runViceProgramToVerifiedTerminal[25: CPU/decimalmode/adc11.prg] 12.01 s
runViceProgramToVerifiedTerminal[26: CPU/decimalmode/adc12.prg] 11.92 s
runViceProgramToVerifiedTerminal[27: CPU/decimalmode/arr00.prg] 12.05 s
runViceProgramToVerifiedTerminal[28: CPU/decimalmode/arr01.prg] 12.03 s
runViceProgramToVerifiedTerminal[29: CPU/decimalmode/arr02.prg] 11.91 s
runViceProgramToVerifiedTerminal[30: CPU/decimalmode/arr10.prg] 11.93 s
runViceProgramToVerifiedTerminal[31: CPU/decimalmode/arr11.prg] 12.02 s
runViceProgramToVerifiedTerminal[32: CPU/decimalmode/arr12.prg] 12.03 s
runViceProgramToVerifiedTerminal[33: CPU/decimalmode/sbc00.prg] 12.02 s
runViceProgramToVerifiedTerminal[34: CPU/decimalmode/sbc01.prg] 12.03 s
runViceProgramToVerifiedTerminal[35: CPU/decimalmode/sbc02.prg] 12.00 s
runViceProgramToVerifiedTerminal[36: CPU/decimalmode/sbc10.prg] 11.93 s
runViceProgramToVerifiedTerminal[37: CPU/decimalmode/sbc11.prg] 12.02 s
runViceProgramToVerifiedTerminal[38: CPU/decimalmode/sbc12.prg] 11.91 s
runViceProgramToVerifiedTerminal[39: CPU/decimalmode/sbcEB00.prg] 12.26 s
runViceProgramToVerifiedTerminal[40: CPU/decimalmode/sbcEB01.prg] 12.27 s
runViceProgramToVerifiedTerminal[41: CPU/decimalmode/sbcEB02.prg] 12.24 s
runViceProgramToVerifiedTerminal[42: CPU/decimalmode/sbcEB10.prg] 12.33 s
runViceProgramToVerifiedTerminal[43: CPU/decimalmode/sbcEB11.prg] 12.27 s
runViceProgramToVerifiedTerminal[44: CPU/decimalmode/sbcEB12.prg] 12.30 s
runViceProgramToVerifiedTerminal[45: CPU/decimalmode/isc00.prg] 11.90 s
runViceProgramToVerifiedTerminal[46: CPU/decimalmode/isc01.prg] 11.95 s
runViceProgramToVerifiedTerminal[47: CPU/decimalmode/isc02.prg] 12.03 s
runViceProgramToVerifiedTerminal[48: CPU/decimalmode/isc03.prg] 11.92 s
runViceProgramToVerifiedTerminal[49: CPU/decimalmode/isc10.prg] 11.89 s
runViceProgramToVerifiedTerminal[50: CPU/decimalmode/isc11.prg] 12.03 s
runViceProgramToVerifiedTerminal[51: CPU/decimalmode/isc12.prg] 12.03 s
runViceProgramToVerifiedTerminal[52: CPU/decimalmode/isc13.prg] 11.94 s
runViceProgramToVerifiedTerminal[53: CPU/decimalmode/rra00.prg] 12.04 s
runViceProgramToVerifiedTerminal[54: CPU/decimalmode/rra01.prg] 11.95 s
runViceProgramToVerifiedTerminal[55: CPU/decimalmode/rra02.prg] 12.04 s
runViceProgramToVerifiedTerminal[56: CPU/decimalmode/rra03.prg] 12.03 s
runViceProgramToVerifiedTerminal[57: CPU/decimalmode/rra10.prg] 12.02 s
runViceProgramToVerifiedTerminal[58: CPU/decimalmode/rra11.prg] 11.92 s
runViceProgramToVerifiedTerminal[59: CPU/decimalmode/rra12.prg] 12.00 s
runViceProgramToVerifiedTerminal[60: CPU/decimalmode/rra13.prg] 11.94 s
runViceProgramToVerifiedTerminal[61: CPU/decimalmode/scanner.prg] 121.9 s
runViceProgramToVerifiedTerminal[62: CPU/hmc6502/AllSuiteA.prg] 12.72 s
runViceProgramToVerifiedTerminal[63: CPU/jsrselfmod/jsr.prg] 11.94 s
runViceProgramToVerifiedTerminal[64: CPU/sha/shaabsy1.prg] 12.33 s
runViceProgramToVerifiedTerminal[65: CPU/sha/shazpy1.prg] 12.05 s
runViceProgramToVerifiedTerminal[66: CPU/shs/shsabsy1.prg] 12.23 s

MOS6526TodDividerTest(C64)

fiftyHzModeAdvancesAfterFiveInputPulses 0 s
switchingAfterFifthPulseSkipsTheImminentIncrement 0 s
switchingAfterFourthPulseAllowsTheNextIncrement 0 s
sixtyHzModeAdvancesAfterSixInputPulses 0 s

WolfgangLorentzTest(C64)

testDisk1 501.4 s
testDisk2
+ [ Detail ]
 330.7 s
testDisk3
+ [ Detail ]
 21.15 s

ViceVICTest(C64)

highResolutionSpriteSpriteCollisionsMatchViceReference 14.01 s
spriteSpriteHiMcMatchesViceReference 12.31 s
spriteGraphicsHiHiMatchesViceReference 12.13 s
spriteSpriteMcMcMatchesViceReference 12.65 s
spriteGraphicsMcHiMatchesViceReference 12.14 s
spriteGraphicsHiMcMatchesViceReference 12.20 s
spriteGraphicsMcMcMatchesViceReference 12.14 s
spriteSpriteMcHiMatchesViceReference 12.65 s
ciaTriggeredLightPenIrqLatency 11.97 s

ViceInterruptOracleTest(C64C)

repeatingProgramRequiresTwoProgressChanges 0 s
terminalGreenRequiresCorrectPcAndHold 0 s
transientGreenNeverPasses 0 s
referenceMismatchNeverPassesAndResetsHold 0 s
exitRecognizerRequiresPublishedIoExitAndSelfJump 0.008 s
schedulerResetIsNeverSilentlyAccepted 0 s

SidTuneTest(C64)

loadPSidTest 12.25 s
detectSidModelTest 16.75 s
loadPrgTest 12.35 s
loadMusStereoTest 10.81 s
loadMusTest 10.43 s
loadPSid3SidTest 11.61 s
loadPSidStereoTest 10.89 s
loadP00Test 10.40 s

ViceInterruptTest(C64C)

verifyInterruptProgram[0: IRQ dummy instruction fetch] 13.61 s
verifyInterruptProgram[1: simultaneous CIA IRQ/NMI] 18.33 s
verifyInterruptProgram[2: branch IRQ recognition] 12.83 s
verifyInterruptProgram[3: branch NMI recognition] 13.16 s
verifyInterruptProgram[4: CIA interrupt acknowledgement IRQ] 12.81 s
verifyInterruptProgram[5: CIA interrupt acknowledgement NMI] 12.80 s
verifyInterruptProgram[6: CIA1 near-IRQ acknowledgement] 12.38 s
verifyInterruptProgram[7: CIA2 near-NMI acknowledgement] 12.04 s
verifyInterruptProgram[8: VIC IRQ acknowledgement via RMW] 15.80 s
verifyInterruptProgram[9: pending unacknowledged VIC IRQ after RTI] 11.99 s
verifyInterruptProgram[10: pending VIC IRQ after PLP] 15.38 s
verifyInterruptProgram[11: pending VIC IRQ after CLI/SEI] 12.37 s
verifyInterruptProgram[12: IRQ during DMA, pattern 1] 53.44 s
verifyInterruptProgram[13: IRQ during DMA, sprite pattern 1b] 53.57 s
verifyInterruptProgram[14: IRQ during DMA, pattern 2] 53.32 s
verifyInterruptProgram[15: IRQ during DMA, sprite pattern 2b] 53.37 s
verifyInterruptProgram[16: IRQ during DMA, pattern 3] 53.37 s
verifyInterruptProgram[17: IRQ during DMA, sprite pattern 3b] 53.79 s
verifyInterruptProgram[18: IRQ during DMA, pattern 4] 53.28 s
verifyInterruptProgram[19: IRQ during DMA, sprite pattern 4b] 53.49 s
verifyInterruptProgram[20: IRQ during DMA, pattern 5] 53.34 s
verifyInterruptProgram[21: IRQ during DMA, sprite pattern 5b] 53.68 s
verifyInterruptProgram[22: IRQ during DMA, pattern 6] 53.32 s
verifyInterruptProgram[23: IRQ during DMA, sprite pattern 6b] 53.58 s
verifyInterruptProgram[24: IRQ during DMA, pattern 7] 53.36 s
verifyInterruptProgram[25: IRQ during DMA, sprite pattern 7b] 53.44 s
verifyInterruptProgram[26: NMI during DMA, pattern 6] 53.71 s
verifyInterruptProgram[27: NMI during DMA, sprite pattern 6b] 53.49 s
verifyInterruptProgram[28: CIA IRQ/NMI delay sweep] 15.44 s
verifyInterruptProgram[29: CIA1 timing, small reload] 13.93 s
verifyInterruptProgram[30: CIA1 timing, one-shot small reload] 14.69 s
verifyInterruptProgram[31: CIA1 timer IRQ 255] 13.56 s
verifyInterruptProgram[32: CIA1 one-shot timer IRQ 255] 14.00 s
verifyInterruptProgram[33: CIA2 timer NMI 255] 13.58 s
verifyInterruptProgram[34: CIA2 one-shot timer NMI 255] 14.28 s
verifyInterruptProgram[35: CIA2 small-latch NMI arrives] 13.57 s
verifyInterruptProgram[36: CIA2 small-latch one-shot NMI arrives] 14.25 s

ViceCpuExitContractTest(C64C)

rejectsMissingOrIncorrectCompletion 0 s
borderBasedExitRequiresUpstreamBranchSignature 0 s
acceptsAcidDisplayRestorationAndFailure 0 s
acceptsXAndYStores 0 s
relocatedJsrRequiresExactMachineCode 0 s
acceptsAccSuccessAndAccFailure 0 s

ViceCIAPortsTest(C64C)

spacePortReadbackAndRelease 14.17 s
ghostingDisplayWithoutKeys 11.84 s
portDirectionsWithoutKeys 12.32 s
ghostingDisplayWithLeftShiftAndRelease 13.92 s
ghostingDisplayWithRightShiftAndRelease 13.52 s
bothShiftsPortReadbackAndRelease 14.24 s
ghostingDisplayWithSpaceAndRelease 13.73 s
rightShiftPortReadbackAndRelease 13.20 s
sdfGhostAppearsInTheDocumentedInputScansAndClearsOnRelease 13.52 s
leftShiftPortReadbackAndRelease 13.20 s

KeyboardGhostingTest(C64)

noKeyReadbacksCoverAllSignedBytePinPatterns 0 s
longChainsReachAFixedPoint 0 s
originalCiaPortsReferenceTablesStillMatch 0 s
disconnectedComponentsDoNotMerge 0 s
joystickInputsRemainLowAndPropagateThroughContacts 0 s
reverseScanDistinguishesInputsFromDrivenHighOutputs 0 s
shiftLockStillWinsWhereOrdinaryLeftShiftDoesNot 0 s
singleContactsRetainTheirDirectReadbacks 0.010 s
readsNeverAddPhantomKeysToThePhysicalSet 0.001 s
restoreIsNeverTreatedAsAMatrixContact 0 s
releasingAnySdfContactRemovesThePhantom 0 s
sdfGeneratesGhostInBothForwardScanModes 0 s
everyThreeCornerRectangleCompletesThroughTheMatrix 0.004 s
legacyReadOverloadsRemainUsable 0 s
samePortReadsFollowKeyboardConnections 0 s
contentionRequiresTwoDistinctActivelyLowOutputs 0 s

ViceCIAAdditionalContractTest(C64)

sdrNeedsBothCompleteSamplePointers 0.006 s
sdrRejectsSpaceAbortedOrIncompleteBaudSweep 0.001 s
invalidSnapshotsAreRejected 0 s
badOrUnreviewedResourcesFailClosed 0.002 s
greenBeforeCascadeCompletionIsNotSuccess 0 s
cascadeFailureCannotBeHiddenByCyclingGreenBorder 0.031 s
observedLoopBytesMustStillMatch 0 s
timerComparesFirstAndLastOf960Bytes 0.001 s
sdrChecksBothThousandByteResults 0.002 s
ramUnderD7ffNeverActsAsAnExitLatch 0 s
parsedReferenceIsIndependentOfCallerPrgArray 0.001 s
ambiguousCompletionAndTruncatedReferencesAreRejected 0 s
allFourteenNormalSdrVariantsHaveContracts 0.014 s
unusedJmpSelfIsNotTimerCompletion 0 s
sdrPreservesEarlierSweepFailures 0.004 s
cascadeNeedsTerminalSuccessAndFullReference 0.002 s
sdrPrematureGreenAndDataAreNotCompletion 0 s
missingFileIsNotSkipped 0 s
changedIdentityIsRejectedEvenAtCompletion 0 s
resultOwnsNoLiveMemoryAndReportsMismatchAddress 0.001 s
timerRequiresAllEightConfigurations 0.001 s
timerSourceFailureCannotBecomePass 0.001 s

ViceCIAPortsTest(C64)

spacePortReadbackAndRelease 14.43 s
ghostingDisplayWithoutKeys 12.01 s
portDirectionsWithoutKeys 12.23 s
ghostingDisplayWithLeftShiftAndRelease 13.43 s
ghostingDisplayWithRightShiftAndRelease 13.46 s
bothShiftsPortReadbackAndRelease 13.44 s
ghostingDisplayWithSpaceAndRelease 13.34 s
rightShiftPortReadbackAndRelease 13.82 s
sdfGhostAppearsInTheDocumentedInputScansAndClearsOnRelease 13.22 s
leftShiftPortReadbackAndRelease 13.44 s

ViceVICTest(C64C)

highResolutionSpriteSpriteCollisionsMatchViceReference 13.88 s
spriteSpriteHiMcMatchesViceReference 12.55 s
spriteGraphicsHiHiMatchesViceReference 12.09 s
spriteSpriteMcMcMatchesViceReference 12.60 s
spriteGraphicsMcHiMatchesViceReference 12.14 s
spriteGraphicsHiMcMatchesViceReference 12.36 s
spriteGraphicsMcMcMatchesViceReference 12.09 s
spriteSpriteMcHiMatchesViceReference 12.51 s
ciaTriggeredLightPenIrqLatency 11.84 s

ViceCpuExitContractTest(C64)

rejectsMissingOrIncorrectCompletion 0 s
borderBasedExitRequiresUpstreamBranchSignature 0 s
acceptsAcidDisplayRestorationAndFailure 0 s
acceptsXAndYStores 0 s
relocatedJsrRequiresExactMachineCode 0 s
acceptsAccSuccessAndAccFailure 0 s

Failure Details

[Summary] [Package List] [Test Cases]


testDisk1
- skipped: WolfgangLorentz requires C64Model.C64
testDisk2
- skipped: WolfgangLorentz requires C64Model.C64
testDisk3
- skipped: WolfgangLorentz requires C64Model.C64
testDisk2
- java.lang.AssertionError
-
cpu.Testsuite.WolfgangLorentzTest(C64):
testDisk3
- java.lang.AssertionError
-
cpu.Testsuite.WolfgangLorentzTest(C64):